High performance integrated circuits (ICs) have gained wide acceptance and utility in present day computing and telecommunications applications. Consumer demand has resulted in increasing functionality and speed of ICs, which is made possible by the steady shrinking of transistor feature sizes. These smaller transistors offer performance benefits, such as faster speed of operation and lower power, as well as lower cost. However, smaller features result in physical effects that must be compensated for in the processing of the IC device, and these compensating processes can introduce reliability concerns.
The reduction of transistor size demands reduction of transistor feature dimensions, such as the gate oxide thickness, Tox, and gate and channel length. Reduction of Tox is necessary to raise the capacitance of the gate as the transistor threshold voltage, Vt, is reduced as the transistor is scaled down. However, the channel length of state-of-the-art metal oxide semiconductor field effect transistors (MOSFETs) has been reduced to dimensions at which short channel effects have an increasing effect on transistor performance. This effect leads to a higher transistor Vt than would otherwise be necessary from scaling alone, and requires an increasing gate electric field strength, Eox, with each transistor technology generation.
Higher Eox results in greater stress on the gate dielectric and on the interface between the gate dielectric and the channel. The quality of this interface is critical to the reliability of the transistor, as changes at the interface can cause undesirable changes of the transistor performance characteristics, such as increased Vt and off current, and decreased saturated drain current and transconductance. These effects occur primarily on p-MOSFETS (equivalently known as p-channel MOSFETS), and are known as Negative Bias Temperature Instability, or NBTI.
NBTI is produced by thermal or voltage stress, but their combination is particularly effective in producing the effect. The activation temperature can be as low as 100° C., and the minimum necessary gate field strength is below 6 MV/cm. These are conditions routinely experienced by MOSFET transistors in current generation integrated circuits. The changes in transistor performance can significantly degrade circuit performance by causing changes in circuit timing, resulting in increased error rates or even device failure.
The root cause of NBTI is the formation of trapped charge at the interface between the gate oxide and the channel, which results from the removal of hydrogen at the interface between the channel and the gate dielectric. Hydrogen may be incorporated in the interface fortuitously as a result of hydrogen containing processes during fabrication, and is intentionally introduced at the end of the fabrication process with a forming gas anneal to passivate dangling bonds at the gate oxide-channel interface. These dangling bonds are a consequence of the lattice mismatch between crystalline silicon in the channel and amorphous silicon dioxide in the gate dielectric, and will result in trapped charge at the interface unless suitably passivated.
Several techniques to reduce NBTI are known, including fluorine implantation of the channel and modification of nitrogen content of nitrided gate oxide. Fluorine implantation, while effective at stabilizing the interface, introduces other detrimental effects, such as enhanced boron diffusion in the gate oxide and higher junction leakage. Reducing the nitrogen content of the gate also improves NBTI, but this must be weighed against the benefits of nitriding the gate, such as increased dielectric constant and reduction of boron diffusion through the gate dielectric.
Accordingly, what is needed in the art is a method of fabricating a semiconductor device that reduces NBTI effects while limiting the detrimental effects on transistor performance.